When the clock synchronous type circuit including a plurality of flip-flops (that will be referred below as F/Fs) that operate in synchronization with the reference clock is formed in the semiconductor integrated circuit device such as an ASIC (Application Specific Integrated Circuit), the reference clock is supplied to each of the F/Fs using a plurality of clock buffer circuits for distributing the reference clock.
FIG. 7 is a circuit diagram showing a conventional clock buffer circuit provided for a semiconductor integrated circuit device, and FIG. 8 is a timing diagram showing input and output waveforms for the clock buffer circuit shown in FIG. 7. FIG. 9 is a circuit diagram showing a configuration of clock tree synthesis using the clock buffer circuit shown in FIG. 7.
As shown in FIG. 7, the conventional clock buffer circuit includes a first inverter 5 and a second inverter 6. The first inverter 5 is constituted from a P-channel field-effect transistor (that will be referred below as a P-channel transistor) 51 and an N-channel field-effect transistor (that will be referred below as an N-channel transistor) 52. Gates of the P-channel transistor 51 and the N-channel transistor 52 are interconnected, and drains of the P-channel transistor 51 and the N-channel transistor 52 are interconnected. The P-channel transistor 51 and the N-channel transistor 52 use different types of carriers in channels. The reference clock is input to the respective gates of the P-channel transistor 51 and the N-channel transistor 52. The second inverter 6 for driving a load is constituted from a P-channel transistor 61 and an N-channel transistor 62. The gates of the P-channel transistor 61 and the N-channel transistor 62 are interconnected, and the drains of the P-channel transistor 61 and the N-channel transistor 62 are interconnected. Sources of the P-channel transistors 51 and 61 are connected respectively to a power supply VDD, while the sources of the N-channel transistors 52 and 62 are connected respectively to a ground potential GND.
Since the conventional clock buffer circuit is based on an assumption that the clock buffer circuit is for general-purpose use in a device such as the ASIC, the clock buffer circuit outputs a waveform that is the same as the input reference clock so as to accommodate both the clock synchronous type circuit that operates in synchronization with the rising edge flank of the reference clock and the clock synchronous type circuit that operates in synchronization with the falling edge flank of the reference clock. When the reference clock with a duty cycle of 50% has been input, for example, the clock buffer circuit outputs a pulse train with the duty cycle of 50% having substantially same delays in rise and fall times and with the rising and falling edges flank that are the same as those of an input waveform.
For this reason, in the conventional clock buffer circuit, the P-channel transistor of each of the inverters is formed to be larger than the N-channel transistor. In other words, the P-channel transistor is formed to have a gate width wider than the N-channel transistor. More specifically, as shown in FIG. 7, the first inverter 5 in a front stage is formed of the P-channel transistor 51 having a gate width Wp of 8.472 μm and the N-channel transistor 52 having a gate width Wn of 2.82 μm, while the second inverter 6 in a back stage is formed of the P-channel transistor 61 having the gate width Wp of 16.944 μm and the N-channel transistor 62 having the gate width Wn of 6.24 μm. A transistor size ratio Wp/Wn of the first inverter 5 then becomes 3.00, while the transistor size ratio of Wp/Wn of the second inverter 6 becomes 2.72. This arrangement is adopted because when a transistor size is the same, the P-channel transistor has lower driving capability than the N-channel transistor.
In the conventional semiconductor integrated circuit device, the clock tree synthesis as shown in FIG. 9, which will be referred to below as CTS, was performed using a clock buffer circuit 50 described above. The clock having same duty ratio and skew is thereby distributed to a plurality of F/Fs provided for the clock synchronous type circuit. FIG. 9 shows an example where posedege F/Fs 60 that operate at the rising edge flank of the reference clock are connected to the CTS.
Patent document 1, for example, proposes a configuration in which the transistor size ratio of the P-channel transistor and the N-channel transistor in a CMOS circuit is made asymmetrical in order to transmit a signal through the semiconductor integrated circuit device at high speed.
[Patent Document 1]
JP Patent Kokai Publication No. JP-A-8-181596